The present disclosure is related to a semiconductor device and, more particularly, to a partially-depleted silicon-on-insulator (SOI) MOSFET.
Manufactures of semiconductor devices continually strive for integrated circuits of higher density and devices of smaller dimensions in order to improve cost efficiencies and performance. However, these scaling efforts have resulted in some undesirable effects in leakage current, e.g., the off-state leakage current (Ioff) of a MOSFET.
Excess leakage current (Ioff) in these MOSFETs may result in high power consumption for devices of large-scale integrated circuits, such as memory, processors, controllers, communication and networking circuits, etc. The high power consumption, in turn, can adversely affect requirements for heat dissipation. Additionally, in the case of some hand-held products, the integrated circuits with excess leakage may reduce the operating-time that may be available within a given fixed-energy battery life. Accordingly, there may be a demand for low-leakage MOSFETs.
Of the bulk and silicon-on-insulator MOSFET, the SOI MOSFET can offer lower parasitic junction capacitance and superior sub-threshold voltage swing. Such benefits may assist high-speed, current drive applications.
In general, SOI MOSFETs can be characterized into two different categories: fully-depleted and partially-depleted SOI MOSFETS. Fully-depleted SOI (FD-SOI) MOSFETs conventionally comprise a very thin body region, which may be fully depleted of majority carries under the influence of a standard gate bias. Partially-depleted SOI (PD-SOI) MOSFETs, on the other hand, may have a thicker body that may not be fully depleted during normal gate bias. This remaining portion that is not depleted may be described as a “floating body” region. Typically, the partially-depleted versus fully depleted SOI MOSFET are more commonly used in integrated circuit designs, which may be due to a variety of considerations such as density constraints and their greater ease of manufacturing.